PCI Express Interface
by Michael Bowling, on Dec 15, 2017 3:34:25 PM
PCI Express 3.0 Technical Challenges
UPDATE 4/21/2020: For PCIe Gen 4 vs. Gen 3 slots and updates, read our latest blog on the subject.
Correctly routing PCIe 3.0 signal traces is a design challenge that few companies can handle well, and taking shortcuts in system host board, single board computer, and backplane designs which utilize the PCI Express 3.0 interface will always result in suboptimal system performance.
With new technologies such as blockchain driving demand for flawless communication between components, this simply is no longer an option. Just look at the new blockchain supercomputer in the making and you'll understand just how important PCIe slots are in today's market.
Another great article to read is Blockchain Explained: Part 2 where we cover the technology roadblocks and how high-performance computing manufacturers are trying to cram as many GPUs into a system that can utilize all the PCIe slots it can handle.
For example, with all previous generations of PCI Express it was best practice to keep traces well below 16 inches to insure optimum performance, but the PCIe Gen3 specification makes the length requirement even more restrictive, which is why it’s so important to understand the difference between PCI Express 3.0, 2.0 and 1.1.
- Engineered to standup up to the rigors of industrial and military computing applications
- Designed to support for both industry standard and custom PCI Express plug-in cards
- Built to maximize system deployment flexibility
- Built to last with 7-10 year long-life processor and backplane components all backed by our 5-year product warranty
- Manufactured in our ISO and ITAR facilities located in the United States
The Gen3 specification requires a pre-validation of the link before any data transmission, and if the automatic equalization training cannot establish a reliable link, then it won’t allow the transmission of data at 8Gt/s speeds, resulting in slower than expected card-to-card as well as card-to-SBC data transfers within a typical system design.
These considerations are critical in the design of a backplane, such as the HDB8259, which supports multiple Gen3 high-performance I/O cards inside a single integrated system.
PCIe 3.0, PCIe 2.0, PCIe 1.1 Differences
With silicon for PCI Express® 3.0 released by various chip vendors, it might be a good idea to review the interface differences between PCIe 3.0, PCI Express 2.0 and PCI Express 1.1. Understanding these interface differences will allow for successful use of the latest PCI Express interface technology into embedded applications.
Does it matter that the single board computer / system host board and option card interface is PCI Express version 1.1, 2.0 or even the new PCIe 3.0? Not really, because the basic SBC to option card interconnect functionality is not affected by PCIe version. The reason for this is that the PCI-SIG (Peripheral Component Interconnect Special Interest Group) was forward thinking when PCI Express 1.1 was first developed.
The PCI-SIG built the basic PCIe interconnects in such a manner as to ensure both scalability and backwards compatibility between the differing PCIe interfaces. This critical specification feature enables the computer’s SBC/SHB, embedded motherboard or backplane hardware to operate with just about any PCI Express option card regardless of interface version.
The potential for increased data throughput and performance within any computing platform is the primary difference between the PCI Express 3.0, 2.0 and 1.1 interfaces. A PCI Express 2.0 board installed in an industrial computer will send its data to the system host board twice as fast as older PCI Express 1.1 boards.
The same scenario plays out in an embedded motherboard. If the motherboard is equipped with PCIe 2.0 card slots, then any PCIe 2.0 card placed into one of these slots will send its data to the board’s CPUs twice as fast as in a PCIe 1.1 system. This speed advantage is cumulative and can be critical in high-performance computing applications.
Summary of PCI Express Interface Parameters:
- Base Clock Speed: PCIe 3.0 = 8.0GHz, PCIe 2.0 = 5.0GHz, PCIe 1.1 = 2.5GHz
- Data Rate: PCIe 3.0 = 1000MB/s, PCIe 2.0 = 500MB/s, PCIe 1.1 = 250MB/s
- Total Bandwidth: (x16 link): PCIe 3.0 = 32GB/s, PCIe 2.0 = 16GB/s, PCIe 1.1 = 8GB/s
- Data Transfer Rate: PCIe 3.0 = 8.0GT/s, PCIe 2.0= 5.0GT/s, PCIe 1.1 = 2.5GT/s
PCIe 3.0 features a number of interface architecture improvements, but communicates at the same interface speeds used in PCIe 2.0. PCIe 3.0 achieves twice the communication speeds of PCIe 2.0 through various architecture and protocol management improvements.
Trenton single board computers, such as the BXT7059 and TSB7053, support a wide variety of PCI Express option card interfaces. Embedded motherboards, such as the JXM7031 and WTM7026, feature multiple PCI Express option card slots and the BPG8032 and BPG7087 backplanes are examples of PICMG 1.3 backplanes with built-in PCI Express 2.0 computing hardware support, while the BPX8093 PCIe backplane supports PCI Express 3.0.
Trenton BPG8032 PCI Express Backplane
The BPG8032 PCI Express backplane is ideal for video wall controllers, graphics processing and GPU computing system solutions. This backplane supports one single board computer & seventeen x16 PCI Express I/O option card slots. Each option card slot uses a x16 mechanical connector to maximize system design flexibility. The BPG8032 can take full advantage of PCI Express 2.0’s data throughput capacity when used with Trenton Systems single board computers.
At Trenton, our engineers are recognized for their knowledgeable and innovative approach to crafting industrial computing solutions, including the design, prototyping and manufacturing of embedded system components for mission critical applications. For a quotation or inquiry on products supporting PCI Express, Contact Trenton or call 770-287-3100 or 800-875-6031.